SJ Semiconductor's $700M IPO: China's bet on homegrown AI chip packaging
SMIC spinoff SJ Semiconductor raised ¥4.8B ($700M) for 3D AI chip packaging. Approved for STAR Market. Why advanced packaging is China's path around US export controls.
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TL;DR: SJ Semiconductor, a 2014 joint venture between SMIC and Jiangsu Changjiang Electronics, has received regulatory approval to list on Shanghai's STAR Market and raise ¥4.8 billion ($700 million). Roughly ¥4 billion of that goes directly into a 3D chip packaging facility. The company has already rocketed from a niche player to China's 4th-largest packaging firm, with chiplet-based multi-chip packaging revenue growing from 5.3% of sales in 2022 to over 56% by mid-2025. This is not an ordinary IPO — it is a direct financial instrument of China's chip sovereignty strategy, designed to replicate at commercial scale what US export controls are trying to prevent.
SJ Semiconductor — full name Jiangsu Silicon Integrated Micro-Semiconductor — was founded in 2014 in Jiangyin, Jiangsu Province. Its founding was a calculated joint venture: Semiconductor Manufacturing International Corporation (SMIC), China's national champion foundry, partnered with Jiangsu Changjiang Electronics Technology Group (JCET), the country's largest chip packaging and testing firm. Put another way, two state-backed heavyweights combined their capabilities to build a company specifically targeting advanced packaging for AI and high-performance computing.
The SMIC connection deserves a moment. In 2021, SMIC divested its entire stake — roughly $400 million worth — in SJ Semiconductor. On the surface, this looks like a retreat. In practice, it was a legal maneuver. By the time of the divestiture, SMIC was already on the US Entity List, which places export restrictions on its ability to source American technology. Holding a stake in an advanced packaging company would have created regulatory complications for SJ Semiconductor's technology partnerships and future IPO.
The ownership separation did not break the relationship. SMIC and SJ Semiconductor maintain active manufacturing and packaging cooperation. The companies are operationally intertwined even though equity ties were formally dissolved. SJ Semiconductor processes chips that SMIC fabricates. SMIC customers route advanced packaging requirements through SJ Semiconductor. It is a partnership by another name.
Today, SJ Semiconductor is backed by China's "Big Fund" — the state-sponsored China Integrated Circuit Industry Investment Fund, the primary financial vehicle China uses to subsidize domestic semiconductor development. That backing matters for two reasons: it insulates the company from normal market pressures, and it signals exactly what the Chinese government wants this company to become.
By 2024, Gartner ranked SJ Semiconductor as the world's 10th-largest packaging and testing company. It was also the fastest-growing in the global top 10 by compound annual revenue growth between 2022 and 2024.
The STAR Market listing — approved for March 4, 2026 — is a landmark event for China's semiconductor industry regardless of how SJ Semiconductor's stock performs on opening day.
| Metric | Detail |
|---|---|
| Exchange | Shanghai STAR Market |
| Listing date | March 4, 2026 |
| Fundraising target | ¥4.8 billion (~$700 million USD) |
| Primary use of proceeds | 3D chip packaging production facility (~¥4B) |
| Secondary uses | R&D, working capital, debt repayment |
| Gartner global rank (2024) | 10th largest packaging and testing company |
| China rank (2024) | 4th largest packaging firm |
| Revenue CAGR (2022-2024) | Fastest among global top 10 |
The allocation of roughly ¥4 billion — more than 83% of the total raise — toward a single 3D chip packaging facility tells you precisely what the company is prioritizing. This is not a diversified capital program or a balance sheet cleanup exercise. It is a concentrated bet on one specific technology that China's AI industry currently cannot source domestically at scale.
The STAR Market itself is the right venue for this listing. Launched in 2019 and modeled loosely on the Nasdaq, it was designed specifically to facilitate listings of high-growth, pre-profit technology companies that would struggle on the Main Board. Companies like Cambricon (AI chips), Horizon Robotics (edge AI), and several other semiconductor firms have listed there. SJ Semiconductor joins a cohort of companies positioned as core infrastructure for China's technology independence.
To understand why this IPO matters beyond its dollar size, you need to understand what chip packaging has become.
For most of semiconductor history, packaging was the boring end of chip manufacturing. You made the chip (wafer fabrication), sliced it up (dicing), and then stuck it in a plastic or ceramic housing to protect it and connect it to a circuit board. Packaging was commodity work. The real intellectual property was in the fab.
That understanding became obsolete around 2016 when the limits of Moore's Law started biting hard.
Moore's Law — the observation that transistor counts on a chip double roughly every two years — has slowed dramatically. The physical limits of silicon etching at 3nm and below are pushing up costs and power consumption at every new node. Adding more transistors in a single die is increasingly difficult and expensive.
The industry's answer has been to think differently about physical integration. Instead of cramming more transistors into one chip, you take multiple smaller chips — called chiplets — and package them together so closely and efficiently that they behave as a single integrated unit. The interconnections between chiplets can be as dense as the connections within a chip. The performance gains come not from smaller transistors but from smarter physical assembly.
This is advanced packaging. And it is now where much of the value in AI chip design actually lives.
"Advanced packaging has moved from an afterthought to the primary competitive differentiator in AI chip performance. The companies that master it will control the AI compute stack." — semiconductor industry analyst, quoted widely in 2025 investor reports
For context: NVIDIA's H100 GPU uses CoWoS (Chip-on-Wafer-on-Substrate) advanced packaging from TSMC. AMD's Instinct MI300 relies on heterogeneous 3D stacking. Apple's M-series chips use TSMC's InFO (Integrated Fan-Out) packaging. Without advanced packaging, none of these products exist in their current form.
China can design competitive chips. China can fabricate chips at trailing-edge nodes (28nm and above) without US equipment. What China currently lacks at scale is the advanced packaging infrastructure to assemble those chips into the multi-chiplet systems that AI workloads require.
SJ Semiconductor's IPO is the financial instrument for closing that gap.
The $700 million raise is earmarked almost entirely for 3D chip packaging capacity. Here is what that actually means.
2D packaging is the baseline. Chips sit flat on a substrate, connected to each other by long wire bonds or solder bumps, with data traveling relatively long distances. Bandwidth is limited. Latency is high.
2.5D packaging stacks chiplets side-by-side on an interposer — a silicon or organic layer that connects them with very dense wiring. TSMC's CoWoS is the gold standard. Data moves between chiplets over short, high-bandwidth paths. This is how the H100 connects its compute die to HBM memory.
3D packaging goes vertical. Chips are literally stacked on top of each other, connected by through-silicon vias (TSVs) — microscopic holes drilled through the silicon with metal conductors running through them. Memory can sit directly on top of a compute die. The distance data must travel collapses to micrometers. Bandwidth explodes. Power drops. It is the most demanding and most valuable technique in the industry.
| Technology | Layout | Key advantages | China capability |
|---|---|---|---|
| Wire bonding (legacy) | Flat, wire connections | Low cost, mature | Strong |
| Flip-chip | Flat, solder bumps | Better signal, denser | Strong |
| 2.5D / Interposer | Side-by-side chiplets | High bandwidth, HBM-compatible | Limited |
| 3D stacking / TSV | Vertical, chip-on-chip | Maximum bandwidth, lowest power | Building |
| Fan-out WLP | Embedded dies, no substrate | Thin form factor, mobile | Moderate |
SJ Semiconductor offers 2.5D and 3D integrated circuits, heterogeneous integration, and fan-out wafer-level packaging. The new facility will materially expand its 3D stacking and heterogeneous integration capacity — the capabilities most directly relevant to AI chip assembly.
The chiplet-based multi-chip packaging revenue surge — from 5.3% of total revenue in 2022 to over 56% by mid-2025 — reflects real market demand, not accounting maneuvers. Customers are routing AI chip packaging work to SJ Semiconductor because the company has built the capability to handle it. The IPO funds the infrastructure to do so at much larger scale.
The US export control strategy targeting China's semiconductor industry has operated on a straightforward thesis: deny China access to the equipment needed to fabricate chips below 14nm, and you limit its ability to produce competitive AI hardware.
That thesis has a structural vulnerability. Export controls target fabrication nodes. They do not — cannot, practically — restrict advanced packaging with the same precision.
The reasoning is technical. Chip packaging equipment is dual-use in ways that leading-edge fab equipment is not. Bonding tools, interposer manufacturing systems, and TSV drilling equipment serve both advanced AI applications and legacy consumer electronics. Controlling them without destroying the global electronics supply chain is politically and technically difficult.
This creates a path. China cannot manufacture H100-class chips. But if it can design competitive chiplets at 14nm or 28nm (both domestically achievable), assemble them using advanced packaging into multi-chiplet AI accelerators, and deploy those systems in data centers — the gap closes considerably. Not entirely, not immediately, but meaningfully.
The US recognized this risk and has steadily expanded controls. The October 2022 rules targeted advanced fab equipment. The October 2023 rules expanded to include more chip designs and added new country restrictions. The 2025 diffusion rules further constrained where chips manufactured using US technology can be sold. But advanced packaging equipment has remained, by and large, accessible.
Beijing's response has been to accelerate domestic investment in exactly this layer of the stack. The Big Fund, which has deployed over $50 billion across China's semiconductor industry since 2014, has explicitly prioritized packaging and testing as a domestic capability gap to close.
SJ Semiconductor is the highest-profile execution of that strategy to reach the public markets.
China's semiconductor industrial policy has adopted the term "More than Moore" — a concept borrowed from the International Roadmap for Devices and Systems — to describe a path to competitive AI hardware that does not require leading-edge process nodes.
The standard framing of chip performance improvement has long been "More Moore" — smaller transistors, denser chips, more compute per unit area. US export controls make that path difficult for China at the frontier.
"More than Moore" takes a different route. Rather than pushing to smaller nodes, it focuses on system-level integration: combining multiple chips into a package that delivers more performance than any single die could achieve. Advanced packaging is the core enabling technology.
This is not a consolation strategy. TSMC, which has no peer globally in leading-edge fabrication, has invested heavily in CoWoS and SoIC (System on Integrated Chips) advanced packaging because the industry consensus is that packaging is where the next decade of performance gains will come from. AMD's Zen architecture wins partly because of chiplet-based packaging. Apple's M-series success is inseparable from InFO packaging.
China is betting that by mastering this layer, it can assemble competitive AI compute systems from domestically fabricated chips — even if those chips are not at the leading edge of process technology.
The logic is credible. The execution is the hard part.
Key milestones in China's "More than Moore" buildout:
| Year | Development |
|---|---|
| 2014 | SJ Semiconductor founded (SMIC + JCET joint venture) |
| 2019 | Big Fund Phase II launched (~$28B+ target) |
| 2021 | SMIC divests SJ Semiconductor stake; regulatory separation |
| 2022 | Chiplet packaging = 5.3% of SJ Semiconductor revenue |
| 2024 | SJ Semiconductor reaches global top 10 (Gartner) |
| Mid-2025 | Chiplet packaging = 56%+ of SJ Semiconductor revenue |
| Mar 2026 | SJ Semiconductor STAR Market IPO, ¥4.8B raised |
| 2026-2027 | New 3D packaging facility operational (est.) |
SJ Semiconductor does not operate in a vacuum. It faces formidable competition from established global leaders and must simultaneously serve China's domestic AI needs while the global packaging market continues to evolve.
TSMC is the dominant force in advanced packaging for AI chips. CoWoS capacity — critical for HBM-integrated AI accelerators — is so constrained that NVIDIA, AMD, and other major chip designers have faced allocation limits. TSMC is investing aggressively in CoWoS expansion in Taiwan and exploring additional capacity internationally. SJ Semiconductor cannot match TSMC's technology depth or scale in the near term.
ASE Technology (Taiwan) and Amkor Technology (US/Korea) are the global leaders in traditional packaging and are both expanding into advanced formats. ASE controls roughly 25% of global outsourced semiconductor assembly and test revenue. Amkor is TSMC's primary Western packaging partner.
China domestic peers. JCET — SJ Semiconductor's founding parent — remains China's largest packaging firm and is itself investing in advanced formats. Tianshui Huatian and Tongfu Microelectronics round out the domestic top tier. All three have received Big Fund backing and are expanding capabilities. SJ Semiconductor's advantage is its SMIC supply chain integration and its concentration on AI-specific packaging rather than general-purpose assembly.
The differentiation that matters most for SJ Semiconductor is customer fit. China's domestic AI chip designers — Cambricon, Biren Technology, Enflame, and others — need packaging partners that can work within a China-only supply chain. They cannot route chips to TSMC's CoWoS line without triggering US review. SJ Semiconductor is positioned as the domestic equivalent: technically capable, politically safe, and backed by the state.
The SJ Semiconductor IPO is a signal, not just an event. Several implications are worth tracking.
For global packaging companies. The market SJ Semiconductor is addressing — AI chip advanced packaging in China — is large and growing. China's domestic AI compute buildout, driven by companies like Huawei, Alibaba, Baidu, and ByteDance, requires packaging capacity. If SJ Semiconductor captures a disproportionate share of that captive market, it limits the serviceable addressable market for global peers like ASE and Amkor within China. Neither of those companies discloses China revenue specifically, but China has historically been a significant portion of both.
For advanced packaging equipment makers. Companies supplying the equipment SJ Semiconductor will use in its new facility — bonders, interposer tools, TSV systems — stand to benefit. The key suppliers are largely Japanese (Tokyo Electron, Shinkawa, Besi) and Dutch (Besi also operates extensively in Asia). US equipment controls have not uniformly restricted packaging equipment, making this a more open market than leading-edge fab equipment.
For China's AI hardware ecosystem. A higher-capacity, domestically controlled packaging layer reduces one of the key bottlenecks in China's AI chip supply chain. Chip designers who could not previously achieve HBM-integrated, multi-chiplet designs at scale domestically may be able to do so within 18-24 months of the new facility becoming operational. This accelerates the timeline for competitive domestic AI accelerators.
For investors tracking geopolitical risk. The STAR Market listing makes SJ Semiconductor accessible to domestic Chinese retail and institutional investors, but restrictions on foreign ownership of Chinese STAR Market listings limit direct exposure for most Western funds. The indirect play is through equipment suppliers, material companies, and the competitive dynamics imposed on global packaging peers.
The critical uncertainty is whether SJ Semiconductor can execute at the technology depth required. Listing on the STAR Market and raising capital are the easy parts. Building a 3D packaging facility that consistently produces multi-chiplet AI packages at competitive yield rates is genuinely hard. TSMC has spent decades developing the process controls and equipment integration required. SJ Semiconductor is moving fast, but the gap in institutional knowledge and process maturity is real.
"Access to capital has never been China's binding constraint in semiconductors. Process knowledge, yield optimization, and ecosystem depth are the hard problems. Money accelerates progress; it does not guarantee it." — widely attributed framing in semiconductor investment analysis
SJ Semiconductor is a chip packaging and testing company headquartered in Jiangyin, Jiangsu Province, China. It was founded in 2014 as a joint venture between SMIC (China's largest foundry) and JCET (China's largest packaging firm). SMIC divested its entire stake in 2021 for regulatory reasons, though the two companies maintain operational cooperation. SJ Semiconductor is currently backed by China's "Big Fund" state semiconductor investment vehicle and other institutional investors.
The STAR Market (Science and Technology Innovation Board) is a Nasdaq-style exchange operated by the Shanghai Stock Exchange, launched in 2019 specifically to facilitate listings of high-growth technology companies. It uses a registration-based system rather than the approval-based system of China's Main Boards, making it more accessible to pre-profit or recently profitable tech companies. SJ Semiconductor joins a cohort of semiconductor and AI hardware companies listed there, including Cambricon.
US export controls primarily target semiconductor fabrication equipment at leading-edge nodes (below 14nm). Advanced packaging equipment — used to assemble multiple chiplets into a single high-performance package — is harder to restrict without disrupting the global electronics supply chain. China can fabricate competitive chiplets at 14nm or 28nm using domestic or non-US equipment, then assemble them using advanced 3D packaging into AI accelerators that collectively deliver more performance than any single die. This "More than Moore" path does not fully replicate leading-edge chips, but it meaningfully closes the performance gap.
3D chip packaging stacks chips vertically on top of each other, connected by through-silicon vias (TSVs) — conductive channels drilled through the silicon. This dramatically shortens the distance data must travel between a compute die and memory, increasing bandwidth and reducing power consumption. For AI workloads that require enormous memory bandwidth (training large language models, running inference at scale), 3D packaging is not a nice-to-have — it is a prerequisite for competitive performance. NVIDIA's H100 and H200 achieve their memory bandwidth through advanced packaging, not raw die design alone.
Not yet, at least not at scale. TSMC's CoWoS (Chip-on-Wafer-on-Substrate) packaging is the industry benchmark, and CoWoS capacity is so constrained that NVIDIA and AMD have faced allocation limits. SJ Semiconductor offers 2.5D and 3D packaging capabilities, but its process maturity, yield rates at production volumes, and the breadth of chiplet configurations it can handle are all below TSMC's level. The new ¥4 billion facility is meant to close that gap. Whether it does depends on execution over the next 18-24 months.
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